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e november 1996 order number: 290532-004 n effective zero wait-state performance up to 33 mhz ? synchronous pipelined reads n smartvoltage technology ? user-selectable 3.3v or 5v v cc ? user-selectable 5v or 12v v pp n 0.33 mb/sec write transfer rate n configurable x8 or x16 operation n 56-lead tsop and ssop type i package n backwards-compatible with 28f008sa command-set n 2 a typical deep power-down n 1 ma typical active i cc current in static mode n 16 separately-erasable/lockable 128-kbyte blocks n 1 million erase cycles per block n state-of-the-art 0.6 m etox? iv flash technology intels 28f016xs 16-mbit flash memory is a revolutionary architecture which is the ideal choice for designing truly revolutionary high-performance products. combining very high read performance with the intrinsic nonvolatility of flash memory, the 28f016xs eliminates the traditional redundant memory paradigm of shadowing code from a slow nonvolatile storage source to a faster execution memory, such as dram, for improved system performance. the i nnovative capabilities of the 28f016xs enable the design of direct- execute code and mass storage data/file flash memory systems. the 28f016xs is the highest performance high-density nonvolatile read/program flash memory solution available today. its synchronous pipelined read interface, flexible v cc and v pp voltages, extended cycling, fast program and read performance, symmetrically-blocked architecture, and selective block locking provide a highly flexible memory component suitable for resident flash component arrays on the system board or simms. the synchronous pipelined interface and x8/x16 architecture of the 28f016xs allow easy interface with minimal glue logic to a wide range of processors/buses, providing effective zero wait-state read performance up to 33 mhz. the 28f016xss dual read voltage allows the same component to operate at either 3.3v or 5.0v v cc . programming voltage at 5v v pp minimizes external circuitry in minimal-chip, space critical designs, while the 12.0v v pp option maximizes program/erase performance. its high read performance combined with flexible block locking enable both storage and execution of operating systems/ application software and fast access to large data tables. the 28f016xs is manufactured on intels 0.6 m etox iv process technology. 28f016xs 16-mbit (1 mbit x 16, 2 mbit x 8) synchronous flash memory
copyright ? intel corporation, 1996 cg-041493 information in this document is provided in connection with intel products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liability or warranties relating to fitness for a particular purpose, merchantabili ty, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. the 28f016xs may contain design defects or errors known as errata. current characterized errata are available upon request. *third-party brands and names are the property of their respective owners. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are referenced in this document, or other intel literature, may be obtained from: intel corporation p.o. box 7641 mt. prospect, il 60056-7641 or call 1-800-879-4683
e 28f016xs flash memory 3 contents page page 1.0 introduction ............................................ 7 1.1 product overview ........................................ 7 2.0 device pinout........................................... 10 2.1 lead descriptions ...................................... 12 3.0 memory maps ........................................... 14 3.1 extended status register memory map..... 15 4.0 bus operations, commands and status register definitions............. 16 4.1 bus operations for word-wide mode (byte# = v ih )........................................... 16 4.2 bus operations for byte-wide mode (byte# = v il ) ........................................... 17 4.3 28f008sa compatible mode command bus definitions.......................................... 18 4.4 28f016xsenhanced command bus definitions ................................................. 19 4.5 compatible status register ....................... 20 4.6 global status register ............................... 21 4.7 block status register ................................ 22 4.8 device configuration code ........................ 23 4.9 sfi configuration table ............................. 23 5.0 electrical specifications ................. 24 5.1 absolute maximum ratings ....................... 24 5.2 capacitance............................................... 24 5.3 transient input/output reference waveforms............................................... 26 5.4 dc characteristics (v cc = 3.3v) ................ 27 5.5 dc characteristics (v cc = 5.0v) ................ 30 5.6 timing nomenclature ................................. 33 5.7 ac characteristicsread only operations ................................................ 34 5.8 ac characteristics for we#controlled write operations ....................................... 40 5.9 ac characteristics for ce x #controlled write operations ....................................... 44 5.10 power-up and reset timings .................. 48 5.11 erase and program performance............. 49 6.0 mechanical specifications ................ 51 appendix a: device nomenclature and ordering information .................................. 53 appendix b: additional information............... 54
28f016xs flash memory e 4 revision history number description -001 original version -002 removed support of the following features: all page buffer operations (read, write, programming, upload device information) command queuing software sleep and abort erase all unlocked blocks and two-byte write ry/by# configuration as part of the device configuration command changed definition of nc. removed no internal connection to die from description. added xx to upper byte of command (data) definition in sections 4.3 and 4.4. modified parameters v and i of section 5.1 to apply to nc pins. increased i ppr (v pp read current) for v pp > v cc to 200 a at v cc = 3.3v/5.0v. changed v cc = 5.0v dc characteristics (section 5.5) marked with note 1 to indicate that these currents are specified for a cmos rise/fall time (10% to 90%) of <5 ns and a ttl rise/fall time of <10 ns. corrected t phch (rp# high to clk) to be a min specification at v cc = 3.3v/5.0v. corrected the graphical representation of t whch and t ehch in figures 15 and 16. increased typical byte/word program times (t whrh1a /t whrh1b ) for v pp = 5.0v (sec. 5.13): t whrh1a from 16.5 s to 29.0 s and t whrh1b from 24.0 s to 35.0 s at v cc = 3.3v t whrh1a from 11.0 s to 20.0 s and t whrh1b from 16.0 s to 25.0 s at v cc = 5.0v. increased typical block program times (t whrh2 / t whrh3 ) for v pp = 5.0v (section 5.13): t whrh2 from 2.2 sec to 3.8 sec and t whrh3 from 1.6 sec to 2.4 sec at v cc = 3.3v t whrh2 from 1.6 sec to 2.8 sec and t whrh3 from 1.2 sec to 1.7 sec at v cc = 5.0v. changed time from erase suspend command to wsm ready spec name to erase suspend latency time to read; modified typical values and added min/max values at v cc =3.3/5.0v and v pp =5.0/12.0v (section 5.13). minor cosmetic changes throughout document. -003 added 3/5# pin to pinout configuration (figure 2), product overview (section 1.1) and lead descriptions (section 2.1) modified block diagram (figure 1): removed address counter; added 3/5# pin added 3/5# pin to test conditions of i ccs specifications added 3/5# pin (y) to timing nomenclature (section 5.6) removed note 7 of section 5.7 modified device configuration code: incorporated ry/by# configuration (level mode support only) modified power-up and reset timings (section 5.10) to include 3/5# pin: removed t 5vph and t 3vph specifications; added t plyl , t plyh , t ylph , and t yhph specifications added ssop pinout (figure 2) and mechanical specifications corrected tsop mechanical specification a1 from 0.50 mm to 0.050 mm (section 6.0) minor cosmetic changes throughout document.
e 28f016xs flash memory 5 revision history (continued) number description -004 require all v cc tolerences to be within 5% of operational voltage i ppes is pushed to 200 a from 50 max i ccd is pushed to 10 a from 5 max updated t avav at 3.3v updated t eleh at 3.3v and 5.0v
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e 28f016xs flash memory 7 1.0 introduction the documentation of the intel 28f016xs flash memory device includes this datasheet, a detailed users manual, a number of application notes and design tools, all of which are referenced in appendix b. the datasheet is intended to give an overview of the chip feature-set and of the operating ac/dc specifications. the 16-mbit flash product family user's manual provides complete descriptions of the user modes, system interface examples and detailed descriptions of all principles of operation. it also contains the full list of software algorithm flowcharts, and a brief section on compatibility with the intel 28f008sa. significant 28f016xs feature revisions occurred between datasheet revisions 290532-001 and 290532-002. these revisions center around removal of the following features: all page buffer operations (read, write, programming, upload device information) command queuing software sleep and abort erase all unlocked blocks and two-byte write ry/by# configuration options in addition, a significant 28f016xs change occurred between datasheet revisions 290532-002 and 290532-003. this change centers around the addition of a 3/5# pin to the devices pinout configuration. figures 2 and 3 show the 3/5# pin assignment for the tsop and ssop type i packages. intel recommends that all customers obtain the latest revisions of 28f016xs documentation. 1.1 product overview the 28f016xs is a high-performance, 16-mbit (16,777,216-bit) block erasable nonvolatile random access memory organized as either 1 mword x 16 or 2 mbyte x 8, subdivided into even and odd banks. address a 1 makes the bank selection. the 28f016xs includes sixteen 128-kbyte (131,072 byte) blocks or sixt een 64-kword (65,536 word) blocks. chip memory maps for x8 and x16 modes are shown in figures 4 and 5. the implementation of a new architecture, with many enhanced features, will improve the device operating characteristics and result in greater product reliability and ease-of-use as compared to other flash memories. significant features of the 28f016xs as compared to previous asynchronous flash memories include: synchronous pipelined read interface significantly improved read and program performance smartvoltage technology ? selectable 3.3v or 5.0 v cc ? selectable 5.0v or 12.0 v pp block program/erase protection the 28f016xss synchronous pipelined interface dramatically raises read performance far beyond previously attainable levels. addresses are synchronously latched and data is read from a 28f016xs bank every 30 ns (5v v cc , sfi configuration = 2). this capability translates to zero wait-state reads at clock rates up to 33 mhz at 5v v cc , after an initial address pipeline fill delay and assuming even and odd banks within the flash memory are alternately accessed. data is latched and driven valid 20 ns (t chqv ) after a rising clk edge. the 28f016xs is capable of operating up to 50 mhz (5v v cc ); its programmable sfi configuration enables system design flexibility, optimizing the 28f016xs to a specific system clock frequency. see section 4.9, sfi configuration table, for specific sfi configurations for given operating frequencies. the sfi configuration optimizes the 28f016xs for a wide range of system operating frequencies. the default sfi configuration is 4, which allows system boot from the 28f016xs at any frequency up to 50 mhz at 5v v cc . after initiating an access, data is latched and begins driving on the data outputs after a clk count corresponding to the sfi configuration has elapsed. the 28f016xs will hold data valid until ce# or oe# is deactivated or a clk count corresponding to the sfi configuration for a subsequent access has elapsed. the clk and adv# inputs, new to the 28f016xs in comparison to previous flash memories, control address latching and device synchronization during read operations. the clk input controls the device latencies, times out the sfi configuration counter and synchronizes data outputs. adv# indicates the presence of a valid address on the 28f016xs
28f016xs flash memory e 8 address inputs. during read operations, addresses are latched and accesses are initiated on a rising clk edge in conjunction with adv# low. both clk and adv# are ignored by the 28f016xs during command/data write sequences. the 28f016xs incorporates smartvoltage technology, providing v cc operation at both 3.3v and 5.0v and program and erase capability at v pp = 12.0v or 5.0v. operating at v cc = 3.3v, the 28f016xs consumes less than one half the power consumption at 5.0v v cc , while 5.0v v cc provides highest read performance capability. v pp operation at 5.0v eliminates the need for a separate 12.0v converter, while the v pp = 12.0v option maximizes program/erase performance. in addition to the flexible program and erase voltages, the dedicated v pp gives complete code protection with v pp v pplk . a 3/5# input pin configures the devices internal circuitry for optimal 3.3v or 5.0v read/program operation. a command user interface (cui) serves as the system interface betw een the microprocessor or microcontroller and the internal memory operation. internal algorithm automation allows program and block erase operations to be executed using a two- write command sequence to the cui in the same way as the 28f008sa 8-mbit flashfile? memory. software locking of memory blocks is an added feature of the 28f016xs as compared to the 28f008sa. the 28f016xs provides selectable block locking to protect code or data such as direct- executable operating systems or application code. each block has an associated nonvolatile lock-bit which determines the lock status of the block. in addition, the 28f016xs has a master write protect pin (wp#) which prevents any modifications to memory blocks whose lock-bits are set. writing of memory data is performed in either byte or word increments, typically within 6 s at 12.0v v pp , which is a 33% improvement over the 28f008sa. a block erase operation erases one of the 16 blocks in typically 1.2 sec, i ndependent of the other blocks. each block can be written and erased a minimum of 100,000 cycles. systems can achieve one million block erase cycles by providing wear-leveling algorithms and graceful block retirement. these techniques have already been employed in many flash file systems and hard disk drive designs. all operations are started by a sequence of write commands to the device. three status registers (described in detail later in this datasheet) and a ry/by# output pin provide information on the progress of the requested operation. the following status registers are used to provide device and wsm operation information to the user: a compatible status register (csr) which is 100% compatible with the 28f008sa flashfile memory status register. the csr, when used alone, provides a straightforward upgrade capability to the 28f016xs from a 28f008sa- based design. a global status register (gsr) which also informs the system of overall write state machine (wsm) status. 16 block status registers (bsrs) which provide block-specific status information such as the block lock-bit status. the gsr and bsr memory maps for byte-wide and word-wide modes are shown in figures 5 and 6. the 28f016xs incorporates an open drain ry/by# output pin. this feature allows the user to or-tie many ry/by# pins together in a multiple memory configuration such as a resident flash array. the 28f016xs also incorporates a dual chip- enable function with two input pins, ce 0 # and ce 1 #. these pins have exactly the same functionality as the regular chip-enable pin, ce#, on the 28f008sa. for minimum chip designs, ce 1 # may be tied to ground and system logic may use ce 0 # as the chip enable input. the 28f016xs uses the logical combination of these two signals to enable or disable the entire chip. both ce 0 # and ce 1 # must be active low to enable the device. if either one becomes inactive, the chip will be disabled. this feature, along with the open drain ry/by# pin, allows the system desi gner to reduce the number of control pins used in a large array of 16-mbit devices.
e 28f016xs flash memory 9 4/15/97 9:41 am 9053204.doc intel confidential (until publication date) output buffer output buffer input buffer input buffer i/o logic id register csr esrs data comparator cui wsm program/erase voltage switch address register input buffer output multiplexer gnd dq 8-15 dq 0-7 ce # ce # oe# we# wp# rp# v cc v ry/by# pp a 0-20 data register 1 0 clk adv# y gating/sensing odd bank y gating/sensing even bank y decoder x decoder even address latch y decoder x decoder odd address latch block 0 128-kbyte block 1 128-kbyte block 14 128-kbyte block 15 128-kbyte byte# 3/5# 3/5# 0532_01 figure 1. 28f016xs block diagram architectural evolution includes synchronous pipelined read interface, smartvoltage technology, and extended status registers
28f016xs flash memory e 10 the byte# pin allows either x8 or x16 read/programs to the 28f016xs. byte# at logic low selects 8-bit mode with address a 0 selecting between low byte and high byte. on the other hand, byte# at logic high enables 16-bit operation with address a 1 becoming the lowest order address and address a 0 is not used (dont care). a device block diagram is shown in figure 1. the 28f016xs incorporates an automatic power saving (aps) feature, which substantially reduces the active current when the device is in static mode of operation (addresses not switching). in aps mode, the typical i cc current is 1 ma at 5.0v (3 ma at 3.3v). a deep power-down mode of operation is invoked when the rp# (called pwd# on the 28f008sa) pin transitions low. this mode brings the device power consumption to less than 2.0 a, typically, and provides additional write protection by acting as a device reset pin during power transitions. a reset time of 300 ns (5v v cc ) is required from rp# switching high before latching an address into the 28f016xs. in the deep power-down state, the wsm is reset (any current operation will abort) and the csr, gsr and bsr registers are cleared. a cmos standby mode of operation is enabled when either ce 0 # or ce 1 # transitions high and rp# stays high with all input control pins at cmos levels. in this mode, the device typically draws an i cc standby current of 70 a at 5v v cc . the 28f016xs is available in 56-lead, 1.2 mm thick, 14 mm x 20 mm tsop and 1.8 mm thick, 16 mm x 23.7 mm ssop type i packages. the form factor and pinout of these two packages allow for very high board layout densities. 2.0 device pinout the 28f016xs is pinout compatible with the 28f016sa/sv 16-mbit flashfile memory com- ponents, providing a performance upgrade path to the 28f016xs. the 28f016xs 56-lead tsop and ssop pinout configurations are shown in figures 2 and 3. ce # 1 28f016sa/sv 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 56 55 53 54 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 e28f016xs 56-lead tsop pinout 14 mm x 20 mm top view 3/5# 3/5# nc wp# we# oe# ry/by# gnd gnd dq 7 dq 14 dq 6 dq 13 dq 5 dq 12 dq 4 dq 11 dq 3 dq 10 byte# adv# clk dq 2 dq 9 dq 1 dq 8 dq 0 a 0 dq 15 v cc v cc a 17 a 18 a 19 a 20 v cc a 15 a 14 a 13 a 12 v pp rp# a 11 a 10 a 9 gnd a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 16 28f016sa/sv a 8 wp# we# oe# ry/by# gnd gnd dq 7 dq 14 dq 6 dq 13 dq 5 dq 12 dq 4 dq 11 dq 3 dq 10 byte# nc nc dq 2 dq 9 dq 1 dq 8 dq 0 a 0 dq 15 v cc v cc ce # 0 nc a 17 a 18 a 19 a 20 v cc a 15 a 14 a 13 a 12 v pp rp# a 11 a 10 a 9 a 8 gnd a 7 a 6 a 5 a 4 a 3 a 2 a 1 ce # 1 a 16 ce # 0 0532_02 figure 2. 28f016xs 56-lead tsop pinout configuration shows compatibility with the 28f016sa/sv, allowing for easy performance upgrades from existing 16-mbit designs
e 28f016xs flash memory 11 4/15/97 9:41 am 9053204.doc intel confidential (until publication date) nc ry/by# we# wp# oe# gnd da28f016xs 56-lead ssop standard pinout 16 mm x 23.7 mm top view 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 a 12 ce # 0 a 13 a 14 a 15 ce # 1 a 18 a 17 a 16 v cc a 20 a 19 v cc dq 13 dq 5 dq 4 dq 12 dq 6 dq 14 dq 7 dq 15 rp# gnd byte# adv# clk gnd dq 10 dq 3 dq 11 dq 0 a 0 dq 8 dq 1 dq 9 v cc a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 9 a 10 a 11 v pp 3/5# 28f016sa/sv 3/5# nc we# wp# oe# gnd a 12 ce # 0 a 13 a 14 a 15 ce # 1 a 20 a 19 a 18 a 17 a 16 v cc v cc ry/by# dq 13 dq 5 dq 12 dq 4 dq 6 dq 14 dq 7 dq 15 28f016sa/sv rp# gnd byte# nc nc gnd dq 10 dq 3 dq 11 dq 0 dq 8 dq 1 dq 9 v cc a 8 a 10 a 11 v pp dq 2 dq 2 a 7 a 4 a 3 a 2 a 1 a 9 a 5 a 6 a 0 xs_ssop figure 3. 28f016xs 56-lead ssop pinout configuration shows compatibility with the 28f016sa/sv, allowing for easy performance upgrades from existing 16-mbit designs
28f016xs flash memory e 12 2.1 lead descriptions symbol type name and function a 0 input byte-select address: selects between high and low byte when device is in x8 mode. this address is latched in x8 data programs and ignored in x16 mode (i.e., the a 0 input buffer is turned off when byte# is high). a 1 input bank-select address: selects an even or odd bank in a selected block. a 128-kbyte block is subdivided into an even and odd bank. a 1 = 0 selects the even bank and a 1 = 1 selects the odd bank, in both byte-wide mode and word- wide mode device configurations. a 2 Ca 16 input word-select addresses: select a word within one 128-kbyte block. address a 1 and a 7 C16 select 1 of 2048 rows, and a 2 C6 select 16 of 512 columns. these addresses are latched during both data reads and programs. a 17 Ca 20 input block-select addresses: select 1 of 16 erase blocks. these addresses are latched during data programs, erase and lock-block operations. dq 0 Cdq 7 input/ output low-byte data bus: inputs data and commands during cui write cycles. outputs array, identifier or status data in the appropriate read mode. floated when the chip is de-selected or the outputs are disabled. dq 8 Cdq 15 input/ output high-byte data bus: inputs data during x16 data program operations. outputs array or identifier data in the appropriate read mode; not used for status register reads. outputs floated when the chip is de-selected, the outputs are disabled (oe# = v ih ) or byte# is driven active. ce 0 #, ce 1 # input chip enable inputs: activate the devices control logic, input buffers, decoders and sense amplifiers. with either ce 0 # or ce 1 # high, the device is de-selected and power consumption reduces to standby levels upon completion of any current data program or erase operations. both ce 0 # and ce 1 # must be low to select the device. all timing specifications are the same for both signals. device selection occurs with the latter falling edge of ce 0 # or ce 1 #. the first rising edge of ce 0 # or ce 1 # disables the device. rp# input reset/power-down: rp# low places the device in a deep power-down state. all circuits that consume static power, even those circuits enabled in standby mode, are turned off. when returning from deep power-down, a recovery time of t phch is required to allow these circuits to power-up. when rp# goes low, the current wsm operation is terminated, and the device is reset. all status registers return to ready, clearing all status flags. exit from deep power-down places the device in read array mode. oe# input output enable: drives device data through the output buffers when low. the outputs float to tri-state off when oe# is high. ce x # overrides oe#, and oe# overrides we#. we# input write enable: controls access to the cui, data register and address latch. we# is active low, and latches both address and data (command or array) on its rising edge.
e 28f016xs flash memory 13 4/15/97 9:41 am 9053204.doc intel confidential (until publication date) 2.1 lead descri p tions (continued) symbol type name and function clk input clock: provides the fundamental timing and internal operating frequency. clk latches input addresses in conjunction with adv#, times out the desired output sfi configuration as a function of the clk period, and synchronizes device outputs. clk can be slowed or stopped with no loss of data or synchronization. clk is ignored during program operations. adv# input address valid: indicates that a valid address is present on the address inputs. adv# low at the rising edge of clk latches the address on the address inputs into the flash memory and initiates a read access to the even or odd bank depending on the state of a 1 . adv# is ignored during program operations. ry/by# open drain output ready/busy: indicates status of the internal wsm. when low, it indicates that the wsm is busy performing an operation. ry/by# high indicates that the wsm is ready for new operations, erase is suspended, or the device is in deep power-down mode. this output is always active (i.e., not floated to tri-state off when oe# or ce 0 #, ce 1 # are high). wp# input write protect: erase blocks can be locked by writing a nonvolatile lock-bit for each block. when wp# is low, those locked blocks as reflected by the block-lock status bits (bsr.6), are protected from inadvertent data programs or erases. when wp# is high, all blocks can be written or erased regardless of the state of the lock-bits. the wp# input buffer is disabled when rp# transitions low (deep power-down mode). byte# input byte enable: byte# low places device in x8 mode. all data is then input or output on dq 0 C7 , and dq 8 C15 float. address a 0 selects between the high and low byte. byte# high places the device in x16 mode, and turns off the a 0 input buffer. address a 1 then becomes the lowest order address. 3/5# input 3.3/5.0 volt select: 3/5# high configures internal circuits for 3.3v operation. 3/5# low configures internal circuits for 5.0v operation. note: reading the array with 3/5# high in a 5.0v system could damage the device. reference the power-up and reset timings (section 5.10) for 3/5# switching delay to valid data. v pp supply program/erase power supply (12.0v 0.6v, 5.0v 0.5v) : for erasing memory array blocks or writing words/bytes into the flash array. v pp = 5.0v 0.5v eliminates the need for a 12.0v converter, while the 12.0v 0.6v option maximizes program/erase performance. successful completion of program and erase attempts is inhibited with v pp at or below 1.5v. program and erase attempts with v pp between 1.5v and 4.5v, between 5.5v and 11.4v, and above 12.6v produce spurious results and should not be attempted. v cc supply device power supply (3.3v 5%, 5.0v 5%): to switch 3.3v to 5.0v (or vice versa), first ramp v cc down to gnd, and then power to the new v cc voltage. do not leave any power pins floating.
28f016xs flash memory e 14 2.1 lead descri p tions (continued) symbol type name and function gnd supply ground for all internal circuitry: do not leave any ground pins floating. nc no connect: lead may be driven or left floating. 3.0 memory maps 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 128-kbyte block 128-kbyte block 128-kbyte block 128-kbyte block 128-kbyte block 128-kbyte block 128-kbyte block 128-kbyte block 128-kbyte block 128-kbyte block 128-kbyte block 128-kbyte block 128-kbyte block 128-kbyte block 128-kbyte block 128-kbyte block x8 mode 000000 1fffff 1bffff 1c0000 1dffff 1e0000 19ffff 1a0000 17ffff 180000 15ffff 160000 13ffff 140000 11ffff 120000 0fffff 100000 0dffff 0e0000 0bffff 0c0000 09ffff 0a0000 07ffff 080000 05ffff 060000 03ffff 040000 01ffff 020000 a 20-0 0532_03 figure 4. 28f016xs memory map (byte-wide mode) 64-kword block 64-kword block 64-kword block 64-kword block 64-kword block 64-kword block 64-kword block 64-kword block 64-kword block 64-kword block 64-kword block 64-kword block 64-kword block 64-kword block 64-kword block 64-kword block 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 x16 mode fffff 00000 effff f0000 dffff e0000 cffff d0000 bffff c0000 affff b0000 9ffff a0000 8ffff 90000 7ffff 80000 6ffff 70000 5ffff 60000 4ffff 50000 3ffff 40000 2ffff 30000 1ffff 20000 0ffff 10000 a 20-1 0532_04 figure 5. 28f016xs memory map (word-wide mode)
e 28f016xs flash memory 15 4/15/97 9:41 am 9053204.doc intel confidential (until publication date) 3.1 extended status register memory map 1e0004h 1e0003h 1e0002h 1e0000h 1e0001h 1e0005h 1e0006h 000004h 000003h 000002h 000000h 000001h 000006h 000005h 01ffffh reserved gsr reserved bsr 0 reserved reserved reserved a 20-0 x8 mode . . . reserved 1fffffh reserved gsr reserved bsr 15 reserved reserved 0532_05 figure 6. extended status register memory map (byte-wide mode) 00002h 00000h 00001h 00003h 0ffffh reserved gsr reserved bsr 0 reserved reserved reserved f0002h f0000h f0001h f0003h reserved gsr reserved bsr 15 reserved reserved a 20-1 x16 mode . . . reserved fffffh 0532_06 figure 7. extended status register memory map (word-wide mode)
28f016xs flash memory e 16 4.0 bus operations, commands and status register definitions 4.1 bus operations for word-wide mode (byte# = v ih ) mode notes rp# ce 0 C1 # oe# we# adv# clk a 1 dq 0C15 ry/by# latch read address 1,9,10 v ih v il xv ih v il - xx x inhibit latching read address 1,9 v ih v il xv ih v ih - xx x read 1,2,7,9 v ih v il v il v ih x - xd out x output disable 1,6,7,9 v ih v il v ih v ih x x x high z x standby 1,6,7,9 v ih v il xxxxx high z x deep power-down 1,3 v il x xxxxx high z v oh manufacturer id 1,4,9 v ih v il v il v ih x - v il 0089h v oh device id 1,4,8,9 v ih v il v il v ih x - v ih 66a8h v oh write 1,5,6,9 v ih v il v ih v il xxxd in x notes: 1. x can be v ih or v il for address or control pins except for ry/by#, which is either v ol or v oh , or high z or d out for data pins depending on whether or not oe# is active. 2. ry/by# output is open drain. when the wsm is ready, erase is suspended, or the device is in deep power-down mode, ry/by# will be at v oh if it is tied to v cc through a resistor. ry/by# at v oh is independent of oe# while a wsm operation is in progress. 3. rp# at gnd 0.2v ensures the lowest deep power-down current. 4. a 0 and a 1 at v il provide device manufacturer codes in x8 and x16 modes respectively. a 0 and a 1 at v ih provide device id codes in x8 and x16 modes respectively. all other addresses are set to zero. 5. commands for erase, data program, or lock-block operations can only be completed successfully when v pp = v pph1 or v pp = v pph2 . 6. while the wsm is running, ry/by# stays at v ol until all operations are complete. ry/by# goes to v oh when the wsm is not busy or in erase suspend mode. 7. ry/by# may be at v ol while the wsm is busy performing various operations (for example, a status register read during a write operation). 8. the 28f016xs shares an identical device identifier with the 28f016xd. 9. ce 0 C1 # at v il is defined as both ce 0 # and ce 1 # low, and ce 0C1 # at v ih is defined as either ce 0 # or ce 1 # high. 10. addresses are latched on the rising edge of clk in conjunction with adv# low. address a 1 = 0 selects the even bank and a 1 = 1 selects the odd bank, in both byte-wide mode and word-wide mode device configurations.
e 28f016xs flash memory 17 4/15/97 9:41 am 9053204.doc intel confidential (until publication date) 4.2 bus operations for byte-wide mode (byte# = v il ) mode notes rp# ce 0 C1 # oe# we# adv# clk a 0 dq 0C7 ry/by# latch read address 1,9,10 v ih v il xv ih v il - xx x inhibit latching read address 1,9 v ih v il xv ih v ih - xx x read 1,2,7,9 v ih v il v il v ih x - xd out x output disable 1,6,7,9 v ih v il v ih v ih x x x high z x standby 1,6,7,9 v ih v ih xxxxx high z x deep power-down 1,3 v il x xxxxx high z v oh manufacturer id 1,4,9 v ih v il v il v ih x - v il 89h v oh device id 1,4,8,9 v ih v il v il v ih x - v ih a8h v oh write 1,5,6,9 v ih v il v ih v il xxxd in x notes: 1. x can be v ih or v il for address or control pins except for ry/by#, which is either v ol or v oh , or high z or d out for data pins depending on whether or not oe# is active. 2. ry/by# output is open drain. when the wsm is ready, erase is suspended, or the device is in deep power-down mode, ry/by# will be at v oh if it is tied to v cc through a resistor. ry/by# at v oh is independent of oe# while a wsm operation is in progress. 3. rp# at gnd 0.2v ensures the lowest deep power-down current. 4. a 0 and a 1 at v il provide device manufacturer codes in x8 and x16 modes respectively. a 0 and a 1 at v ih provide device id codes in x8 and x16 modes respectively. all other addresses are set to zero. 5. commands for erase, data program, or lock-block operations can only be completed successfully when v pp = v pph1 or v pp = v pph2 . 6. while the wsm is running, ry/by# stays at v ol until all operations are complete. ry/by# goes to v oh when the wsm is not busy or in erase suspend mode. 7. ry/by# may be at v ol while the wsm is busy performing various operations (for example, a status register read during a program operation). 8. the 28f016xs shares an identical device identifier with the 28f016xd. 9. ce 0 C1 # at v il is defined as both ce 0 # and ce 1 # low, and ce 0C1 # at v ih is defined as either ce 0 # or ce 1 # high. 10. addresses are latched on the rising edge of clk in conjunction with adv# low. address a 1 = 0 selects the even bank and a 1 = 1 selects the odd bank, in both byte-wide mode and word-wide mode device configurations.
28f016xs flash memory e 18 4.3 28f008sa compatible mode command bus definitions first bus cycle second bus cycle command notes oper addr data (4) oper addr data (4) read array write x xxffh read aa ad intelligent identifier 1 write x xx90h read ia id read compatible status register 2 write x xx70h read x csrd clear status register 3 write x xx50h program write x xx40h write pa pd alternate program write x xx10h write pa pd block erase/confirm write x xx20h write ba xxd0h erase suspend/resume write x xxb0h write x xxd0h address data aa = array address ad = array data ba = block address csrd = csr data ia = identifier address id = identifier data pa = program address pd = program data x = dont care notes: 1. following the intelligent identifier command, two read operations access the manufacturer and device signature codes. 2. the csr is automatically available after device enters data program, erase, or suspend operations. 3. clears csr.3, csr.4 and csr.5. also clears gsr.5 and all bsr.5, bsr.4 and bsr.2 bits. see status register definitions. 4. the upper byte of the data bus (d 8 C15 ) during command writes is a dont care in x16 operation of the device.
e 28f016xs flash memory 19 4/15/97 9:41 am 9053204.doc intel confidential (until publication date) 4.4 28f016xs enhanced command bus definitions first bus cycle second bus cycle command notes oper addr data (4) oper addr data (4) read extended status register 1 write x xx71h read ra gsrd bsrd lock block/confirm write x xx77h write ba xxd0h upload status bits/confirm 2 write x xx97h write x xxd0h device configuration 3 write x xx96h write x dccd address data ba = block address ad = array data ra = extended register address bsrd = bsr data pa = program address gsrd = gsr data x = dont care dccd = device configuration code data notes: 1. ra can be the gsr address or any bsr address. see figures 5 and 6 for extended status register memory maps. 2. upon device power-up, all bsr lock-bits come up locked. the upload status bits command must be written to reflect the actual lock-bit status. 3. this command sets the sfi configuration allowing the device to be optimized for the specific sytem operating frequency. 4. the upper byte of the data bus (d 8 C15 ) during command writes is a dont care in x16 operation of the device.
28f016xs flash memory e 20 4.5 compatible status register wsms ess es dws vpps r r r 76543210 notes: csr.7 = write state machine status 1 = ready 0 = busy ry/by# output or wsms bit must be checked to determine completion of an operation (erase, erase suspend, or data program) before the appropriate status bit (ess, es or dws) is checked for success. csr.6 = erase-suspend status 1 = erase suspended 0 = erase in progress/completed csr.5 = erase status 1 = error in block erasure 0 = successful block erase if dws and es are set to 1 during an erase attempt, an improper command sequence was entered. clear the csr and attempt the operation again. csr.4 = data write status 1 = error in data program 0 = data program successful csr.3 = v pp status 1 = v pp error detect, operation abort 0 = v pp ok the vpps bit, unlike an a/d converter, does not provide continuous indication of v pp level. the wsm interrogates v pp ?s level only after the data program or erase command sequences have been entered, and informs the system if v pp has not been switched on. vpps is not guaranteed to report accurate feedback between v pplk (max) and v pph1 (min), between v pph1 (max) and v pph2 (min), and above v pph2 (max). csr.2C0 = reserved for future enhancements these bits are reserved for future use; mask them out when polling the csr.
e 28f016xs flash memory 21 4/15/97 9:41 am 9053204.doc intel confidential (until publication date) 4.6 global status register wsms oss dos r r r r r 76543210 notes: gsr.7 = write state machine status 1 = ready 0 = busy ry/by# output or wsms bit must be checked to determine completion of an operation (block lock, suspend, upload status bits, erase or data program) before the appropriate status bit (oss or dos) is checked for success. gsr.6 = operation suspend status 1 = operation suspended 0 = operation in progress/completed gsr.5 = device operation status 1 = operation unsuccessful 0 = operation successful or currently running gsr.4 C0 = reserved for future enhancements these bits are reserved for future use; mask them out when polling the gsr.
28f016xs flash memory e 22 4.7 block status register bs bls bos r r vpps vppl r 76543210 notes: bsr.7 = block status 1 = ready 0 = busy ry/by# output or bs bit must be checked to determine completion of an operation (block lock, suspend, erase or data program) before the appropriate status bits (bos, bls) is checked for success. bsr.6 = block lock status 1 = block unlocked for program/erase 0 = block locked for program/erase bsr.5 = block operation status 1 = operation unsuccessful 0 = operation successful or currently running bsr.2 = v pp status 1 = v pp error detect, operation abort 0 = v pp ok bsr.1 = v pp level 1 = v pp detected at 5.0v 10% 0 = v pp detected at 12.0v 5% bsr.1 is not guaranteed to report accurate feedback between the v pph1 and v pph2 voltage ranges. programs and erases with v pp between v pplk (max) and v pph1 (min), between v pph1 (max) and v pph2 (min), and above v pph2 (max) produce spurious results and should not be attempted. bsr.4,3,0 = reserved for future enhancements these bits are reserved for future use; mask them out when polling the bsrs.
e 28f016xs flash memory 23 4/15/97 9:41 am 9053204.doc intel confidential (until publication date) 4.8 device configuration code r r sfi2 sfi1 sfi0 r r rb 76543210 notes: dcc.5 Cdcc.3 = sfi configuration (sfi2-sfi0) 001 = sfi configuration 1 010 = sfi configuration 2 011 = sfi configuration 3 100 = sfi configuration 4 (default) default sfi configuration on power-up or return from deep power-down mode is 4, allowing system boot from the 28f016xs at any frequency up to the device's maximum frequency. undocumented combinations of sfi2-sfi0 are reserved by intel corporation for future implementations and should not be used. dcc.0 = ry/by# configuration (rb) 1 = level mode (default) undocumented combinations of rb are reserved by intel corporation for future implementations and should not be used. dcc.7Cdcc.6, dcc.2Cdcc.1 = reserved for future enhancements these bits are reserved for future use. set these bits to 0 when modifying the device configuration code. 4.9 sfi configuration table sfi configuration notes 28f016xs-15 frequency (mhz) 28f016xs-20 frequency (mhz) 28f016xs-25 frequency (mhz) 4 1 50 (and below) 50 (and below) 40 (and below) 3 50 (and below) 37.5 (and below) 30 (and below) 2 33 (and below) 25 (and below) 20 (and below) 1 16.7 (and below) 12.5 (and below) 10 (and below) note: 1. default sfi configuration after power-up or return from deep power-down mode via rp# low.
28f016xs flash memory e 24 5.0 electrical specifications 5.1 absolute maximum ratings* temperature under bias .................... 0c to +80c storage temperature ................... C65c to +125c notice: this is a production datasheet. the specifications are subject to change without notice. verify with your local intel sales office that you have the latest datasheet before finalizing a design. *warning: stressing the device beyond the absolute maximum ratings may cause permanent damage. these are stress ratings only. operation beyond the operating conditions is not recommended and extended exposure beyond the "operating conditions" may affect device reliability. v cc = 3.3v 5% systems symbol parameter notes min max units test conditions t a operating temperature, commercial 1 0 70 c ambient temperature v cc v cc with respect to gnd 2 C0.2 7.0 v v pp v pp supply voltage with respect to gnd 2,3 C0.2 14.0 v v voltage on any pin (except v cc ,v pp ) with respect to gnd 2,5 ?0.5 v cc + 0.5 v i current into any non-supply pin 5 30 ma i out output short circuit current 4 100 ma v cc = 5.0v 5% systems symbol parameter notes min max units test conditions t a operating temperature, commercial 1 0 70 c ambient temperature v cc v cc with respect to gnd 2 C0.2 7.0 v v pp v pp supply voltage with respect to gnd 2,3 C0.2 14.0 v v voltage on any pin (except v cc ,v pp ) with respect to gnd 2,5 ?2.0 7.0 v i current into any non-supply pin 5 30 ma i out output short circuit current 4 100 ma notes: 1. operating temperature is for commercial product defined by this specification. 2. minimum dc voltage is C0.5v on input/output pins. during transitions, this level may undershoot to C2.0v for periods <20 ns. maximum dc voltage on input/output pins is v cc +0.5v which may overshoot to v cc +2.0v for periods <20 ns. 3. maximum dc voltage on v pp may overshoot to +14.0v for periods <20 ns. 4. output shorted for no more than one second. no more than one output shorted at a time. 5. this specification also applies to pins marked nc.
e 28f016xs flash memory 25 4/15/97 9:41 am 9053204.doc intel confidential (until publication date) 5.2 capacitance for a 3.3v 5% system: symbol parameter notes typ max units test conditions c in capacitance looking into an address/control pin 168pft a = +25 c, f = 1.0 mhz c out capacitance looking into an output pin 1 8 12 pf t a = +25 c, f = 1.0 mhz c load load capacitance driven by outputs for timing specifications 1, 2 50 pf for the 28f016xs-20 and 28f016xs-25 for 5.0v 5% system: symbol parameter notes typ max units test conditions c in capacitance looking into an address/control pin 168pft a = +25 c, f = 1.0 mhz c out capacitance looking into an output pin 1 8 12 pf t a = +25 c, f = 1.0 mhz c load load capacitance driven by outputs for timing specifications 1, 2 100 pf for the 28f016xs-20 30 pf for the 28f016xs-15 note: 1. sampled, not 100% tested. guaranteed by design. 2. to obtain ibis models for the 28f016xs, please contact your local intel/distribution sales office.
28f016xs flash memory e 26 5.3 transient input/output reference waveforms test points input output 2.0 0.8 0.8 2.0 2.4 0.45 0532_07 ac test inputs are driven at v oh (2.4 vttl) for a logic 1 and v ol (0.45 vttl) for a logic 0. input timing begins at v ih (2.0 vttl) and v il (0.8 vttl). output timing ends at v ih and v il . input rise and fall times (10% to 90%) <10 ns. figure 8. transient input/output reference waveform (v cc = 5.0v 5%) for standard testing configuration (1) test points input output 1.5 3.0 0.0 1.5 0532_08 ac test inputs are driven at 3.0v for a logic 1 and 0.0v for a logic 0. input timing begins, and output timing ends, at 1.5v. input rise and fall times (10% to 90%) <10 ns. figure 9. transient input/output reference waveform (v cc = 3.3v 5%) high speed reference waveform (2) (v cc = 5.0v 5%) notes: 1. testing characteristics for 28f016xs-20 at 5v v cc . 2. testing characteristics for 28f016xs-15 at 5v v cc and 28f016xs-20/28f016xs-25 at 3.3v v cc .
e 28f016xs flash memory 27 4/15/97 9:41 am 9053204.doc intel confidential (until publication date) 5.4 dc characteristics v cc = 3.3v 5%, t a = 0c to +70c 3/5# = pin set high for 3.3v operations symbol parameter notes min typ max units test conditions i li input load current 1 1av cc = v cc max v in = v cc or gnd i lo output leakage current 1 10 a v cc = v cc max v out = v cc or gnd i ccs v cc standby current 1,5 70 130 a v cc = v cc max ce 0 #, ce 1 #, rp# = v cc 0.2v byte#, wp#, 3/5# = v cc 0.2v or gnd 0.2v 1 4 ma v cc = v cc max ce 0 #, ce 1 #, rp# = v ih byte#, wp#, 3/5# = v ih or v il i ccd v cc deep power-down current 1 2 5 a rp# = gnd 0.2v byte# = v cc 0.2v or gnd 0.2v i ccr 1 v cc word/byte read current 1,4,5 65 85 ma v cc = v cc max cmos: ce 0 # ,ce 1 # = gnd 0.2v, byte# = gnd 0.2v or v cc 0.2v, inputs = gnd 0.2v or v cc 0.2v 4-location access sequence: 3-1-1-1 (clocks) f = 25 mhz, i out = 0 ma i ccr 2 v cc word/byte read current 1,4, 5,6 60 75 ma v cc = v cc max cmos: ce 0 #, ce 1 # = gnd 0.2v, byte# = gnd 0.2v or v cc 0.2v, inputs = gnd 0.2v or v cc 0.2v 4-location access sequence: 3-1-1-1 (clocks) f = 16 mhz, i out = 0 ma
28f016xs flash memory e 28 5.4 dc characteristics (continued) v cc = 3.3v 5%, t a = 0c to +70c 3/5# = pin set high for 3.3v operations symbol parameter notes min typ max units test conditions i ccw v cc program current 1,6 8 12 ma v pp = 12.0v 5% program in progress 817mav pp = 5.0v 10% program in progress i cce v cc block erase current 1,6 6 12 ma v pp = 12.0v 5% block erase in progress 917mav pp = 5.0v 10% block erase in progress i cces v cc erase suspend current 1,2 3 6 ma ce 0 #, ce 1 # = v ih block erase suspended i pps v pp standby/read 1 1 10 a v pp v cc i ppr current 30 200 a v pp > v cc i ppd v pp deep power- down current 1 0.2 5 a rp# = gnd 0.2v i ppw v pp program current 1,6 10 15 ma v pp = 12.0v 5% program in progress 15 25 ma program in progress i ppe v pp erase current 1,6 4 10 ma v pp = 12.0v 5% block erase in progress 14 20 ma v pp = 5.0v 10% block erase in progress i ppes v pp erase suspend current 1 30 200 a v pp = v pph1 or v pph2 block erase suspended v il input low voltage 6 C0.3 0.8 v v ih input high voltage 6 2.0 v cc +0.3 v v ol output low voltage 6 0.4 v v cc = v cc min i ol = 4 ma v oh 1 output high voltage 6 2.4 v v cc = v cc min i oh = C2.0 ma v oh 2v cc C0.2 vv cc = v cc min i oh = C100 a
e 28f016xs flash memory 29 4/15/97 9:41 am 9053204.doc intel confidential (until publication date) 5.4 dc characteristics (continued) v cc = 3.3v 5%, t a = 0c to +70c 3/5# = pin set high for 3.3v operations symbol parameter notes min typ max units test conditions v ppl k v pp erase/program lock voltage 3,6 0.0 1.5 v v pph1 v pp during program/erase operations 3 4.5 5.0 5.5 v v pph2 v pp during program/erase operations 3 11.4 12.0 12.6 v v lko v cc erase/program lock voltage 2.0 v notes: 1. all currents are in rms unless otherwise noted. typical values at v cc = 3.3v, v pp = 12.0v or 5.0v, t = +25c. these currents are valid for all product versions (package and speeds). 2. i cces is specified with the device de-selected. if the device is read while in erase suspend mode, current draw is the sum of i cces and i ccr . 3. block erases, programs and lock block operations are inhibited when v pp v pplk and not guaranteed in the ranges between v pplk (max) and v pph1 (min), between v pph1 (max) and v pph2 (min) and above v pph2 (max). 4. automatic power savings (aps) reduces i ccr to 3 ma typical in static operation. 5. cmos inputs are either v cc 0.2v or gnd 0.2v. ttl inputs are either v il or v ih . 6. sampled, but not 100% tested. guaranteed by design.
28f016xs flash memory e 30 5.5 dc characteristics v cc = 5.0v 5%, t a = 0c to +70c 3/5# = pin set low for 5.0v operations symbol parameter notes min typ max units test conditions i li input load current 1 1 a v cc = v cc max v in = v cc or gnd i lo output leakage current 1 10 a v cc = v cc max v out = v cc or gnd i ccs v cc standby current 1,5 70 130 a v cc = v cc max ce 0 #, ce 1 #, rp# = v cc 0.2v byte#, wp#, 3/5# = v cc 0.2v or gnd 0.2v 2 4 ma v cc = v cc max ce 0 #, ce 1 #, rp# = v ih byte#, wp#, 3/5# = v ih or v il i ccd v cc deep power- down current 1 2 5 a rp# = gnd 0.2v byte# = v cc 0.2v or gnd 0.2v i ccr 1 v cc read current 1,4,5 120 175 ma v cc = v cc max cmos: ce 0 # ,ce 1 # = gnd 0.2v, byte# = gnd 0.2v or v cc 0.2v, inputs = gnd 0.2v or v cc 0.2v 4-location access sequence: 3-1-1-1 (clocks) f = 33 mhz, i out = 0 ma i ccr 2 v cc read current 1,4, 5,6 105 150 ma v cc = v cc max cmos: ce 0 #, ce 1 # = gnd 0.2v, byte# = gnd 0.2v, or v cc 0.2v, inputs = gnd 0.2v or v cc 0.2v 4-location access sequence: 3-1-1-1 (clocks) f = 20 mhz, i out = 0 ma
e 28f016xs flash memory 31 4/15/97 9:41 am 9053204.doc intel confidential (until publication date) 5.5 dc characteristics (continued) v cc = 5.0v 5%, t a = 0c to +70c 3/5# = pin set low for 5.0v operations symbol parameter notes min typ max units test conditions i ccw v cc program current 1,6 25 35 ma v pp = 12.0v 5% program in progress 25 40 ma v pp = 5.0v 10% program in progress i cce v cc erase suspend current 1,6 18 25 ma v pp = 12.0v 5% block erase in progress 20 30 ma v pp = 5.0v 10% block erase in progress i cces v cc block erase current 1,2 5 10 ma ce 0 #, ce 1 # = v ih block erase suspended i pps v pp standby/read 1 1 10 a v pp v cc i ppr current 30 200 a v pp > v cc i ppd v pp deep power- down current 1 0.2 5 a rp# = gnd 0.2v i ppw v pp program current 1,6 7 12 ma v pp = 12.0v 5% program in progress 17 22 ma v pp = 5.0v 10% program in progress i ppe v pp block erase current 1,6 5 10 ma v pp = 12.0v 5% block erase in progress 16 20 ma v pp = 5.0v 10% block erase in progress i ppes v pp erase suspend current 1 30 200 a v pp = v pph1 or v pph2 block erase suspended v il input low voltage 6 C0.5 0.8 v v ih input high voltage 6 2.0 v cc +0.5 v v ol output low voltage 6 0.45 v v cc = v cc min i ol = 5.8 ma v oh 1 output high voltage 6 0.85 v cc vv cc = v cc min i oh = C2.5 ma v oh 2v cc C0.4 v cc = v cc min i oh = C100 a
28f016xs flash memory e 32 5.5 dc characteristics (continued) v cc = 5.0v 5%, t a = 0c to +70c 3/5# = pin set low for 5.0v operations symbol parameter notes min typ max units test conditions v ppl k v pp program/erase lock voltage 3,6 0.0 1.5 v v pph1 v pp during program/erase operations 4.5 5.0 5.5 v v pph2 v pp during program/erase operations 11.4 12.0 12.6 v v lko v cc program/erase lock voltage 2.0 v notes: 1. all currents are in rms unless otherwise noted. typical values at v cc = 5.0v , v pp = 12.0v or 5.0v , t = +25c. these currents are valid for all product versions (package and speeds) and are specified for a cmos rise/fall time (10% to 90%) of <5 ns and a ttl rise/fall time of <10 ns. 2. i cces is specified with the device de-selected. if the device is read while in erase suspend mode, current draw is the sum of i cces and i ccr. 3. block erases, programs and lock block operations are inhibited when v pp v pplk and not guaranteed in the ranges between v pplk (max) and v pph1 (min), between v pph1 (max) and v pph2 (min) and above v pph2 (max). 4. automatic power saving (aps) reduces i ccr to 1 ma typical in static operation. 5. cmos inputs are either v cc 0.2v or gnd 0.2v. ttl inputs are either v il or v ih . 6. sampled, but not 100% tested. guaranteed by design.
e 28f016xs flash memory 33 4/15/97 9:41 am 9053204.doc intel confidential (until publication date) 5.6 timing nomenclature all 3.3v system timings are measured from where signals cross 1.5v. for 5.0v systems, use the st andard jedec cross point definitions (standard testing) or from where signals cross 1.5v (high speed testing). each timing parameter consists of five characters. some common examples are defined below: t elch time(t) from ce# (e) going low (l) to clk (c) going high (h) t avch time(t) from address (a) valid (v) to clk (c) going high (h) t whdx time(t) from we# (w) going high (h) to when the data (d) can become undefined (x) pin characters pin states a address inputs h high c clk (clock) l low d data inputs v valid q data outputs x driven, but not necessarily valid e ce# (chip enable) z high impedance f byte# (byte enable) l latched g oe# (output enable) w we# (write enable) p rp# (deep power-down pin) r ry/by# (ready busy) v adv# (address valid) y 3/5# pin 5v v cc at 4.5v minimum 3v v cc at 3.0v minimum
28f016xs flash memory e 34 5.7 ac characteristics read only operations (1) v cc = 3.3v 5%, t a = 0c to +70c versions (3) 28f016xs-20 28f016xs-25 symbol parameter notes min max min max units f clk clk frequency 50 40 mhz t clk clk period 20 25 ns t ch clk high time 6 8.5 ns t cl clk low time 6 8.5 ns t clch clk rise time 4 4 ns t chcl clk fall time 4 4 ns t elch ce x # setup to clk 6 25 35 ns t vlch adv# setup to clk 20 25 ns t avch address valid to clk 20 25 ns t chax address hold from clk 0 0 ns t chvh adv# hold from clk 0 0 ns t glch oe# setup to clk 20 25 ns t chqv clk to data delay 30 35 ns t phch rp# high to clk 480 480 ns t chqx output hold from clk 2 6 6 ns t elqx ce x # to output low z 2,6 0 0 ns t ehqz ce x # high to output high z 2,6 30 30 ns t glqx oe# to output low z 2 0 0 ns t ghqz oe# high to output high z 2 30 30 ns t oh output hold from ce x # or oe# change, whichever occurs first 60 0 ns
e 28f016xs flash memory 35 4/15/97 9:41 am 9053204.doc intel confidential (until publication date) 5.7 ac characteristics read only operations (1) (continued) v cc = 5.0v 5%, t a = 0c to +70c versions (3) 28f016xs-15 (4) 28f016xs-20 (5) symbol parameter notes min max min max units f clk clk frequency 66 50 mhz t clk clk period 15 20 ns t ch clk high time 3.5 6 ns t cl clk low time 3.5 6 ns t clch clk rise time 4 4 ns t chcl clk fall time 4 4 ns t elch ce x # setup to clk 6 25 30 ns t vlch adv# setup to clk 15 20 ns t avch address valid to clk 15 20 ns t chax address hold from clk 0 0 ns t chvh adv# hold from clk 0 0 ns t glch oe# setup to clk 15 20 ns t chqv clk to data delay 20 30 ns t phch rp# high to clk 300 300 ns t chqx output hold from clk 2 5 5 ns t elqx ce x # to output low z 2,6 0 0 ns t ehqz ce x # high to output high z 2,6 30 30 ns t glqx oe# to output low z 2 0 0 ns t ghqz oe# high to output high z 2 30 30 ns t oh output hold from ce x # or oe# change, whichever occurs first 60 0 ns notes: 1. see ac input/output reference waveforms for timing measurements. 2. sampled, not 100% tested. guaranteed by design. 3. device speeds are defined as: 15 ns at v cc = 5.0v equivalent to 20 ns at v cc = 3.3v 20 ns at v cc = 5.0v equivalent to 25 ns at v cc = 3.3v 4. see the high speed ac input/output reference waveforms. 5. see the standard ac input/output reference waveforms. 6. ce x # is defined as the latter of ce 0 # or ce 1 # going low, or the first of ce 0 # or ce 1 # going high.
28f016xs flash memory e 36 chcl t t clk ch t cl t clch t 0532_09 figure 10. clk waveform clk addr adv# oe# cex# a even even odd data 1 clk periods odd t ghqz 1 t avch t chax t vlch t chvh t elch t glch t glqx t oh t ehqz t chqx t chqv t elqx 0532_10 note: 1. the 28f016xs can sustain an optimized burst access throughout the 28f016xs array assuming alternating bank accesses; the length of the burst access is dictated by the control cpu or bus architecture. figure 11. read timing waveform (1) (sfi configuration = 1, alternate-bank accesses)
e 28f016xs flash memory 37 4/15/97 9:41 am 9053204.doc intel confidential (until publication date) clk addr adv# oe# cex# a even even odd data 2 clk periods odd t ghqz 1 t avch t chax t vlch t chvh t elch t glch t glqx t oh t ehqz t chqx t chqv t elqx 0532_11 note: 1. the 28f016xs can sustain an optimized burst access throughout the 28f016xs array assuming alternating bank accesses; the length of the burst access is dictated by the control cpu or bus architecture. figure 12. read timing waveform (1) (sfi configuration = 2, alternate-bank accesses)
28f016xs flash memory e 38 clk addr adv# oe# cex# a even even odd data 3 clk periods odd t ghqz 1 t avch t chax t vlch t chvh t elch t glch t glqx t oh t ehqz t chqx t chqv note 2 note 2 t elqx 0532_12 notes: 1. the 28f016xs can sustain an optimized burst access throughout the 28f016xs array assuming alternating bank accesses; the length of the burst access is dictated by the control cpu or bus architecture. 2. depending on the actual operation frequency, a consecutive alternating bank access can be initiated one clock period earlier. see ap-398 designing with the 28f016xs for further information. figure 13. read timing waveform (1) (sfi configuration = 3, alternate-bank accesses)
e 28f016xs flash memory 39 4/15/97 9:41 am 9053204.doc intel confidential (until publication date) clk addr adv# oe# cex# a even even odd data 4 clk periods odd t ghqz rp# 1 t avch t chax t vlch t chvh t elch t glch t glqx t oh t ehqz t phch t chqx t chqv t elqx 0532_13 note: 1. the 28f016xs can sustain an optimized burst access throughout the 28f016xs array assuming alternating bank accesses; the length of the burst access is dictated by the control cpu or bus architecture. figure 14. read timing waveform (1) (sfi configuration = 4, alternating bank accesses)
28f016xs flash memory e 40 5.8 ac characteristics for we# controlled write operations (1) v cc = 3.3v 5%, t a = 0c to +70c versions 28f016xs-20 28f016xs-25 symbol parameter notes min typ max min typ max unit t avav write cycle time 75 75 ns t vpwh 1,2 v pp setup to we# going high 3 100 100 ns t phel rp# setup to ce x # going low 3,7 480 480 ns t elwl ce x # setup to we# going low 3,7 0 0 ns t avwh address setup to we# going high 2,6 60 60 ns t dvwh data setup to we# going high 2,6 60 60 ns t wlwh we# pulse width 60 60 ns t whdx data hold from we# high 2 5 5 ns t whax address hold from we# high 25 5 ns t wheh ce x # hold from we# high 3,7 5 5 ns t whwl we# pulse width high 15 15 ns t ghwl read recovery before write 30 0 ns t whrl we# high to ry/by# going low 3 100 100 ns t rhpl rp# hold from valid status register (csr, gsr, bsr) data and ry/by# high 30 0 ns t phwl rp# high recovery to we# going low 3 480 480 ns t whch write recovery before read 20 20 ns t qvvl 1,2 v pp hold from valid status register (csr, gsr, bsr) data and ry/by# high 30 0 s t whqv 1 duration of program operation 3,4, 5,8 5 9 tbd 5 9 tbd s t whqv 2 duration of block erase operation 3,4 0.6 1.6 20 0.6 1.6 20 sec
e 28f016xs flash memory 41 4/15/97 9:41 am 9053204.doc intel confidential (until publication date) 5.8 ac characteristics for we# controlled write operations (1) (continued) v cc = 5.0v 5%, t a = 0c to +70c versions 28f016xs-15 28f016xs-20 symbol parameter notes min typ max min typ max unit t avav write cycle time 65 65 ns t vpwh 1,2 v pp setup to we# going high 3 100 100 ns t phel rp# setup to ce x # going low 3,7 300 300 ns t elwl ce x # setup to we# going low 3,7 0 0 ns t avwh address setup to we# going high 2,6 50 50 ns t dvwh data setup to we# going high 2,6 50 50 ns t wlwh we# pulse width 50 50 ns t whdx data hold from we# high 2 0 0 ns t whax address hold from we# high 25 5 ns t wheh ce x # hold from we# high 3,7 5 5 ns t whwl we# pulse width high 15 15 ns t ghwl read recovery before write 30 0 ns t whrl we# high to ry/by# going low 3 100 100 ns t rhpl rp# hold from valid status register (csr, gsr, bsr) data and ry/by# high 30 0 ns t phwl rp# high recovery to we# going low 3 300 300 ns t whch write recovery before read 20 20 ns t qvvl 1,2 v pp hold from valid status register (csr, gsr, bsr) data and ry/by# high 30 0 s t whqv 1 duration of program operation 3,4, 5,8 4.5 6 tbd 4.5 6 tbd s t whqv 2 duration of block erase operation 3,4 0.6 1.2 20 0.6 1.2 20 sec
28f016xs flash memory e 42 notes: 1. read timings during program and erase are the same as for normal read. 2. refer to command definition tables for valid address and data values. 3. sampled, but not 100% tested. guaranteed by design. 4. program/erase durations are measured to valid status register (csr) data. 5. program operations are typically performed with 1 programming pulse. 6. address and data are latched on the rising edge of we# for all command program operations. 7. ce x # is defined as the latter of ce 0 # or ce 1 # going low, or the first of ce 0 # or ce 1 # going high. 8. please contact intels application hotline or your local sales office for current tbd information.
e 28f016xs flash memory 43 4/15/97 9:41 am 9053204.doc intel confidential (until publication date) v v deep power-down ih il addresses (a) t avav t whax in a read extended status register data write data-write or erase setup command write valid address & data (data-write) or erase confirm command automated data-write or erase delay v v ih il addresses (a) t avav avwh t t whax in a read compatible status register data write read extended register command a=ra note 1 note 2 note 3 avwh t clk note 6 adv# note 6 we# (w) oe# (g) rp# (p) v pp cex # (e) (v) v v ih il v v ih il t wheh elwl t t whdx whwl t v v ih il t wlwh t dvwh v ih il v v ih v il phwl t high z in dd in t t qvvl2 d in il v pph2 v pph1 v t vpwh2 data (d/q) whqv1,2 v v ry/by# (r) t whrl t whch oh ol d in note 4 d out t rhpl t ghwl note 5 pplk v note 7 note 8 t vpwh1 t qvvl1 0532_14 notes: 1. this address string depicts data program/erase cycles with corresponding verification via esrd. 2. this address string depicts data program/erase cycles with corresponding verification via csrd. 3. this cycle is invalid when using csrd for verification during data program/erase operations. 4. ce x # is defined as the latter of ce 0 # or ce 1 # going low or the first of ce 0 # or ce 1 # going high. 5. rp# low transition is only to show t rhpl ; not valid for above read and program cycles. 6. data program/erase cycles are asynchronous; clk and adv# are ignored. 7. v pp voltage during data program/erase operations valid at both 12.0v and 5.0v . 8. v pp voltage equal to or below v pplk provides complete flash memory array protection. figure 15. ac waveforms for we# command write operations, illustrating a two command write sequence followed by an extended status register read
28f016xs flash memory e 44 5.9 ac characteristics for ce x # controlled write operations (1) v cc = 3.3v 5%, t a = 0c to +70c versions 28f016xs-20 28f016xs-25 symbol parameter notes min typ max min typ max unit t avav write cycle time 80 75 ns t vpeh 1,2 v pp setup to ce x # going high 3,7 100 100 ns t phwl rp# setup to we# going low 3 480 480 ns t wlel we# setup to ce x # going low 3,7 0 0 ns t aveh address setup to ce x # going high 2,6,7 60 60 ns t dveh data setup to ce x # going high 2,6,7 60 60 ns t eleh ce x # pulse width 7 65 60 ns t ehdx data hold from ce x # high 2,7 10 10 ns t ehax address hold from ce x # high 2,7 10 10 ns t ehwh we hold from ce x # high 3,7 5 5 ns t ehel ce x # pulse width high 7 15 15 ns t ghel read recovery before write 30 0 ns t ehrl ce x # high to ry/by# going low 3,7 100 100 ns t rhpl rp# hold from valid status register (csr, gsr, bsr) data and ry/by# high 30 0 ns t phel rp# high recovery to ce x # going low 3,7 480 480 ns t ehch write recovery before read 20 20 ns t qvvl 1,2 v pp hold from valid status register (csr, gsr, bsr) data and ry/by# high 30 0 s t ehqv 1 duration of program operation 3,4,5,8 5 9 tbd 5 9 tbd s t ehqv 2 duration of block erase operation 3,4 0.6 1.6 20 0.6 1.6 20 sec
e 28f016xs flash memory 45 4/15/97 9:41 am 9053204.doc intel confidential (until publication date) 5.9 ac characteristics for ce x # controlled write operations (1) (continued) v cc = 5.0v 5%, t a = 0c to +70c versions 28f016xs-15 28f016xs-20 symbol parameter notes min typ max min typ max unit t avav write cycle time 60 60 ns t vpeh 1,2 v pp setup to ce x # going high 3,7 100 100 ns t phwl rp# setup to we# going low 3 300 300 ns t wlel we# setup to ce x # going low 3,7 0 0 ns t aveh address setup to ce x # going high 2,6,7 45 45 ns t dveh data setup to ce x # going high 2,6,7 45 45 ns t eleh ce x # pulse width 7 50 50 ns t ehdx data hold from ce x # high 2,7 0 0 ns t ehax address hold from ce x # high 2,7 5 5 ns t ehwh we hold from ce x # high 3,7 5 5 ns t ehel ce x # pulse width high 7 15 15 ns t ghel read recovery before write 30 0 ns t ehrl ce x # high to ry/by# going low 3,7 100 100 ns t rhpl rp# hold from valid status register (csr, gsr, bsr) data and ry/by# high 30 0 ns t phel rp# high recovery to ce x # going low 3,7 300 300 ns t ehch write recovery before read 20 20 ns t qvvl 1,2 v pp hold from valid status register (csr, gsr, bsr) data and ry/by# high 30 0 s t ehqv 1 duration of program operation 3,4,5,8 4.5 6 tbd 4.5 6 tbd s t ehqv 2 duration of block erase operation 3,4 0.6 1.2 20 0.6 1.2 20 sec
28f016xs flash memory e 46 notes: 1. read timings during write and erase are the same as for normal read. 2. refer to command definition tables for valid address and data values. 3. sampled, but not 100% tested. guaranteed by design. 4. program/erase durations are measured to valid status register (csr) data. 5. program operations are typically performed with 1 programming pulse. 6. address and data are latched on the rising edge of we# for all command write operations. 7. ce x # is defined as the latter of ce 0 # or ce 1 # going low, or the first of ce 0 # or ce 1 # going high. 8. please contact intels application hotline or your local sales office for current tbd information.
e 28f016xs flash memory 47 4/15/97 9:41 am 9053204.doc intel confidential (until publication date) clk note 6 v v deep power-down ih il addresses (a) t avav t ehax in a read extended status register data write data-write or erase setup command write valid address & data (data-write) or erase confirm command automated data-write or erase delay v v ih il addresses (a) t avav aveh t t ehax in a read compatible status register data write read extended register command a=ra note 1 note 2 note 3 aveh t we# (w) oe# (g) rp# (p) v pp cex#(e) (v) v v ih il v v ih il t ehwh wlel t t ehdx ehel t v v ih il t eleh t dveh v ih il v v ih v il phel t high z in dd in t t qvvl2 d in il v pph1 v pph2 v t vpeh2 data (d/q) ehqv1,2 v v ry/by# (r) t ehrl t ehch oh ol d in note 4 d out t rhpl t ghel note 5 pplk v adv# note 6 note 7 note 8 t vpeh1 t qvvl1 0532_15 notes: 1. this address string depicts data program/erase cycles with corresponding verification via esrd. 2. this address string depicts data program/erase cycles with corresponding verification via csrd. 3. this cycle is invalid when using csrd for verification during data program/erase operations. 4. ce x # is defined as the latter of ce 0 # or ce 1 # going low or the first of ce 0 # or ce 1 # going high. 5. rp# low transition is only to show t rhpl ; not valid for above read and program cycles. 6. data program/erase cycles are asynchronous; clk and adv# are ignored. 7. v pp voltage during data program/erase operations valid at both 12.0v and 5.0v . 8. v pp voltage equal to or below v pplk provides complete flash memory array protection. figure 16. ac waveforms for ce x # controlled write operations, illustrating a two command write sequence followed by an extended status register read
28f016xs flash memory e 48 5.10 power-up and reset timings rp# 3/5# 0v 3.3v v power-up cc 5.0v v cc (p) (y) (3v,5v) 4.5v plyl t t pl5v ylph t yhph t 0532_18 note: for read timings following reset see section 5.7. figure 17. v cc power-up and rp# reset waveforms symbol parameter notes min max unit t plyl t plyh rp# low to 3/5# low (high) 0 s t ylph t yhph 3/5# low (high) to rp# high 0 s t pl5v t pl3v rp# low to v cc at 4.5v (minimum) rp# low to v cc at 3v (min) or 3.6v (max) 20 s notes: 1. the t ylph and/or t yhph times must be strictly followed to guarantee all other read and program specifications for the 28f016xs. 2. the power supply may start to switch concurrently with rp# going low.
e 28f016xs flash memory 49 4/15/97 9:41 am 9053204.doc intel confidential (until publication date) 5.11 erase and program performance (3,4) v cc = 3.3v 5%, v pp = 5.0v 5%, t a = 0c to +70c symbol parameter notes min typ (1) max units test conditions t whrh 1a byte program time 2,5 tbd 29 tbd s t whrh 1b word program time 2,5 tbd 35 tbd s t whrh 2 block program time 2,5 tbd 3.8 tbd sec byte program mode t whrh 3 block program time 2,5 tbd 2.4 tbd sec word program mode block erase time 2,5 tbd 2.8 tbd sec erase suspend latency time to read 1.0 12 75 s v cc = 3.3v 5%, v pp = 12.0v 0.6v, t a = 0c to +70c symbol parameter notes min typ (1) max units test conditions t whrh 1 program time 2,5 5 9 tbd s t whrh 2 block program time 2,5 tbd 1.2 4.2 sec byte program mode t whrh 3 block program time 2,5 tbd 0.6 2.0 sec word program mode block erase time 2 0.6 1.6 20 sec erase suspend latency time to read 1.0 955s
28f016xs flash memory e 50 5.11 erase and program performance (3,4) (continued) v cc = 5.0v 5%, v pp = 5.0v 5%, t a = 0c to +70c symbol parameter notes min typ (1) max units test conditions t whrh 1a byte program time 2,5 tbd 20 tbd s t whrh 1b word program time 2,5 tbd 25 tbd s t whrh 2 block program time 2,5 tbd 2.8 tbd sec byte program mode t whrh 3 block program time 2,5 tbd 1.7 tbd sec word program mode block erase time 2,5 tbd 2.0 tbd sec erase suspend latency time to read 1.0 955s v cc = 5.0v 5%, v pp = 12.0v 0.6v, t a = 0c to +70c symbol parameter notes min typ (1) max units test conditions t whrh 1 program time 2,5 4.5 6 tbd s t whrh 2 block program time 2,5 tbd 0.8 4.2 sec byte program mode t whrh 3 block program time 2,5 tbd 0.4 2.0 sec word program mode block erase time 2 0.6 1.2 20 sec erase suspend latency time to read 1.0 740s notes: 1. +25c, and nominal voltages. 2. excludes system-level overhead. 3. these performance numbers are valid for all speed versions. 4. sampled, but not 100% tested. guaranteed by design. 5. please contact intels application hotline or your local sales office for current tbd information.
e 28f016xs flash memory 51 4/15/97 9:41 am 9053204.doc intel confidential (until publication date) 6.0 mechanical specifications 048928.eps figure 18. mechanical specifications of the 28f016xs 56-lead tsop type i package family: thin small out-line package symbol millimeters notes minimum nominal maximum a 1.20 a 1 0.050 a 2 0.965 0.995 1.025 b 0.100 0.150 0.200 c 0.115 0.125 0.135 d 1 18.20 18.40 18.60 e 13.80 14.00 14.20 e 0.50 d 19.80 20.00 20.20 l 0.500 0.600 0.700 n56 ? 0 3 5 y 0.100 z 0.150 0.250 0.350
28f016xs flash memory e 52 e 1 y c a1 b e d see detail a detail a he a r2 a2 r1 l 1 b a 0528_20 figure 19. mechanical specifications of the 28f016sv 56-lead ssop type i package family: shrink small out-line package symbol millimeters notes minimum nominal maximum a 1.80 1.90 a1 0.47 0.52 0.57 a2 1.18 1.28 1.38 b 0.25 0.30 0.40 c 0.13 0.15 0.20 d 23.40 23.70 24.00 e 13.10 13.30 13.50 e 1 0.80 he 15.70 16.00 16.30 n56 l 1 0.45 0.50 0.55 y 0.10 a 2 3 4 b345 r1 0.15 0.20 0.25 r2 0.15 0.20 0.25
e 28f016xs flash memory 53 4/15/97 9:41 am 9053204.doc intel confidential (until publication date) appendix a device nomenclature and ordering information product line designator for all intel flash products package da = ssop e = tsop device type s = synchronous pipelined interface a2 8 f 06 1 xs - 5 1 period of maximum clk input frequency (ns) device density 016 = 16 mbit product family x = fast flash d 0532_20 valid combinations option order code v cc = 3.3v 5%, 50 p f load, 1.5v i/o levels (1) v cc = 5.0v 5%, 100 pf load ttl i/o levels (1) v cc = 5.0v 5%, 30 p f load 1.5v i/o levels (1) 1 e28f016xs15 28f016xs-20 28f016xs-15 2 e28f016xs20 28f016xs-25 28f016xs-20 3 da28f016xs15 28f016xs-20 28f016xs-15 4 da28f016xs20 28f016xs-25 28f016xs-20 note: 1. see section 5.3 for transient input/output reference waveforms.
28f016xs flash memory e 54 appendix b additional information (1,2) order number document/tool 297372 16-mbit flash product family users manual 292147 ap-398 designing with the 28f016xs 292146 ap-600 performance benefits and power/energy savings of 28f016xs- based system designs 292163 ap-610 flash memory in-system code and data update techniques 292165 ab-62 compiled code optimizations for flash memories 297500 interfacing the 28f016xs to the i960 microprocessor family 297504 interfacing the 28f016xs to the intel486? microprocessor family 294016 er-33 etox? flash memory technologyinsight to intels fourth generation process innovation 297508 flashbuilder utility contact intel/distribution sales office 28f016xs benchmark utility contact intel/distribution sales office flash cycling utility contact intel/distribution sales office 28f016xs ibis model contact intel/distribution sales office 28f016xs vhdl model contact intel/distribution sales office 28f016xs timingdesigner* library files contact intel/distribution sales office 28f016xs orcad/viewlogic schematic symbols note: 1. please call the intel literature center at (800) 548-4725 to request intel documentation. international customers should contact their local intel or distribution sales office. 2. visit intels world wide web home page at http://www.intel.com for technical documentation and tools.

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